1. Field of the Invention
The present invention relates to a clock signal generating circuit, and in particular to an analog delay locked loop (DLL) circuit employed for a microprocessor or a synchronous dynamic random access memory (DRAM).
2. Description of the Background Art
As semiconductor memory devices are developed, memory chips are operated in a higher speed. In general, a clock signal generating circuit delays an external clock signal for a predetermined time, and generates an internal clock signal used for the high-speed memory chip. However, there is a limitation to delay the external clock signal. Accordingly, in order to obtain the internal clock signal locked to the external clock signal, a phase locked loop (PLL) circuit or a delay locked loop (DLL) circuit is employed in a high-performance integrated circuit.
As illustrated in FIG. 1, an analog DLL circuit used as a conventional clock signal generating circuit includes a phase detector 100, a charge pump 101, a low pass filter 102, a voltage control delay unit 103 and a driver 104.
The phase detector 100 detects a phase difference between the external clock signal CLKX and the internal clock signal CLKI. The phase detector 100 is a phase detector of an edge triggered method, and may be embodied by an exclusive OR gate XOR, a JK flip-flop and the like. The charge pump 101 carries out a pumping operation according to phase difference signals UP, DN outputted from the phase detector 100. The low pass filter 102 filters an output from the charge pump 101, and outputs a control voltage CV.
The voltage control delay unit 103 includes a plurality of delay cells connected in series, delays the external clock signal CLKX according to the control voltage CV outputted from the low pass filter 102, and outputs a delayed clock signal CLKD. Here, the number of the delay cells may be varied.
Referring to FIG. 2, there is shown a preferable embodiment of the voltage control delay unit 103.
As depicted in FIG. 2, the voltage control delay unit 103 includes: first to third inverters 10.about.12 having PMOS transistors and NMOS transistors, and sequentially delaying the external clock signal CLKX; and PMOS transistors 13.about.16 and NMOS transistors 17.about.20 each respectively connected to sources of the PMOS and NMOS transistors of the first to third inverters 10.about.12, and forming a current mirror. The PMOS transistors 13.about.16 and the NMOS transistors 17.about.20 serve as is load transistors.
The operation of the conventional analog DLL circuit will now be described.
The phase detector 100 compares phases of the two clock signals CLKX, CLKI having an identical frequency. When the phase of the internal clock signal CLKI is faster than that of the external clock signal CLKX, the phase detector 100 outputs the phase difference signal UP. In the case that the phase of the internal clock signal CLKI is slower than that of the external clock signal CLKX, the phase detector 100 outputs the phase difference signal DN. The charge pump 101 carries out the pumping operation according to the phase difference signals UP, DN outputted from the phase detector 100. The low pass filter 102 filters an output from the charge pump 101, and outputs the control voltage CV to the voltage control delay unit 103.
Accordingly, a delay amount of the voltage control delay unit 103 is determined by the control voltage CV. That is, a turn-on degree of the NMOS transistors 17.about.20 is controlled by a level of the control voltage CV, and thus loads of the inverters 10.about.12 are varied by the PMOS transistors 13.about.16 and the NMOS transistors 17.about.20 composing the current mirror. As a result, delay amounts of the inverters 10.about.12 are determined by the varied loads thereof, thereby generating the delay clock signal CLKD.
The driver 104 amplifies the delay clock signal CLKD outputted from the voltage control delay unit 103, and generates the internal clock signal CLKI in order to drive a large load capacitance of an internal circuit (not shown). The internal clock signal CLKI is inputted again into the phase detector 100. Therefore, the conventional analog DLL circuit generates the internal clock signal CLKI locked to the external clock signal CLKX by repeatedly performing the above operation.
However, a jitter is inevitably generated in the clock signal generating circuit (DLL or PLL) generating the internal clock signal having an identical phase to the external clock signal. The high-speed operation of the circuit is limited by a jitter property. Here, an element that influences much on the jitter property is noise resulting from a power supply source. There is also a problem that a circuit operated in a wide frequency region has an inferior jitter property in a low frequency.
In addition, there is an idle state or a stand-by state for reducing a power consumption in the high integrated circuit. When the idle state is converted to an active mode, in order to rapidly recover the clock signal, the clock signal generating circuit (PLL or DLL) must be maintained in an operational state. As a result, a current consumption of the clock signal generating circuit is increased.